The present invention relates to a semiconductor testing apparatus and a semiconductor testing method and, in particular, to a semiconductor testing apparatus and a semiconductor testing method capable of testing precisely the gradation output voltages of a semiconductor integrated circuit having a large number of output terminals each for outputting a multi-level output voltage (gradation output voltage) for driving a liquid crystal display panel or the like.
Description of the Related Art
Driving schemes for liquid crystal display panels (TFT liquid crystal display panels) are classified into two types which are dot inversion scheme and line inversion scheme, depending on the polarity switching scheme of the liquid crystal driving voltage. As for the liquid crystal driving voltage which is outputted from a semiconductor integrated circuit for liquid crystal driving (liquid crystal driving apparatus, hereafter), this voltage is outputted as a DA converted voltage generated by dividing a maximum voltage of 5 V, 13 V, or the like into a predetermined multi-level voltage depending on the display gradation level. For example, in the case of 256-gradation level display, a 512-level driving voltage is outputted in dot inversion scheme, while a 256-level driving voltage is outputted in line inversion scheme.
A liquid crystal driving apparatus according to a prior art is constructed, for example, in the form of a package having 384 pins for driving the three series of R, G, and B each having 128 dots. When a liquid crystal display panel having vertical 1024 dots by horizontal 1280 dots according to SXGA standard is to be driven by any liquid crystal driving apparatus, ten of such liquid crystal driving apparatuses each constructed in the form of a package having 384 pins are to be used. Meanwhile, in the shipment of such liquid crystal driving apparatuses, total inspection is carried out, whereby those not satisfying predetermined specifications are selectively eliminated.
FIG. 17 is a block diagram schematically showing a typical liquid crystal driving apparatus. Gradation display input data RGB (6 bits or more/output in each color) is sampled sequentially, whereby the gradation display input data pieces in the number corresponding to one horizontal period are acquired and latched in a hold memory. After that, each piece of the data is provided through a level shifter to a DA converter (digital-to-analogue converter; abbreviated as a DAC in some cases, hereafter). For each output, the DAC selects a gradation level generated by a reference voltage generation circuit (ladder resistors), and thereby outputs a gradation level (gradation output voltage) through an output operational amplifier provided for each output and through an output terminal.
FIG. 18 is a circuit diagram schematically showing a reference voltage generation circuit. The above-mentioned reference voltage generation circuit generates a desired gradation level as a voltage (V0-Vn) outputted from a resistor connection point by means of the resistor-dividing of a DC voltage Vdc using ladder resistors (R1-Rn). Depending on the above-mentioned input data (the number of bits), a 6-bit DAC permits 64-gradation level display, while an 8-bit DAC permits 256-gradation level display, and while a 10-bit DAC permits 1024-gradation level display. With an increase in the number of gradation levels in liquid crystal driving apparatuses, precise voltage measurement becomes indispensable in the test of liquid crystal driving apparatuses in order to ensure the quality.
That is, a test is necessary for checking whether the gradation output voltages outputted from DACs have correct voltage values and whether the values of the gradation output voltages are uniform among DACs. Further, when the supply voltage to a device to be tested (DUT: device under test) is the same, and when the performance in the output is improved from 64 gradation levels to 256 gradation levels, the precision of the measurement needs to be improved by a factor of four.
A semiconductor testing apparatus (semiconductor test system), a semiconductor testing method, and the like are described below for the case that a DUT to be tested is a liquid crystal driving apparatus (liquid crystal driving LSI) which comprises n-gradation level DACs each for selecting and outputting one from n voltage levels for driving a liquid crystal display panel and which comprises M output terminals for liquid crystal driving.
FIGS. 19 and 20 are block diagrams each showing schematically a prior art semiconductor test system. Such a prior art is disclosed, for example, in JP-A2001-99899. The prior art semiconductor test system of FIG. 19 is composed of a semiconductor testing apparatus (semiconductor tester) 182 for testing a DUT 181. The semiconductor testing apparatus 182 provides a predetermined input signal (not shown) to the DUT 181, and thereby tests (determines) whether the signals converted in a certain manner by the DACs 183 provided in the DUT 181 and then outputted from the output terminals Y1-YM are appropriate or not. In this semiconductor test system, the semiconductor testing apparatus 182 provides predetermined input signals to the DUT (liquid crystal driving apparatus) 181, and thereby causes the DUT to output sequentially the first gradation level signal through the n-th gradation level signal. This output is switched by a matrix switch 184 (ch1-chM) provided in the semiconductor testing apparatus 182, and then inputted to an analogue voltmeter 185. The analogue voltmeter 185 measures sequentially the first gradation level output voltage of each output (output terminals Y1-YM). In each time of the measurement, the result is stored in a data memory 186 provided in the semiconductor testing apparatus 182. This operation is repeated until the n-th gradation level, whereby data for all outputs and all gradation levels is eventually stored in the data memory 186. As a result, data having a size of the number of outputs m (M output terminals)xc3x97n (n gradation levels) is stored in the data memory 186.
The data stored in the data memory 186 is processed by a predetermined operation in an operation apparatus 187 provided in the semiconductor testing apparatus 182, whereby a test is performed on each gradation level output voltage of each output terminal and on the uniformity of the gradation output voltages among the output terminals. In such a test of the liquid crystal driving apparatus (DUT 181), with an increase in the number of outputs and in the number of gradation levels of the liquid crystal driving apparatus, a necessity is occurring for measuring the gradation output voltage values with higher precision. This causes an increase in the testing time, and requires an expensive semiconductor testing apparatus (182) comprising a high precision analogue voltmeter (185).
In the prior art semiconductor test system of FIG. 20, difference voltages are measured between an expected voltage (expected gradation voltage) for each gradation level and the output voltages from respective output terminals (Y1-YM) of the liquid crystal driving apparatus. Determination is performed on these difference voltages in a parallel manner by a comparing section 196. Here, the expected gradation voltage (expected voltage, in some cases hereafter) indicates a voltage expected to be generated depending on each gradation level according to the design. The prior art semiconductor test system of FIG. 20 comprises a DUT 191, a semiconductor testing apparatus 192, expected voltage generating means 60, and a differential amplifier array module 193. The DUT 191 comprises DACs 194. The differential amplifier array module 193 comprises differential amplifiers 195. The semiconductor testing apparatus 192 comprises a comparing section 196. The operation of the DUT 191 and the semiconductor testing apparatus 192 is the same as that of the DUT 181 and the semiconductor testing apparatus 182 of FIG. 19.
The expected voltage generating means 60 generates an expected gradation voltage to be outputted from the DUT 191, that is, an ideal output voltage (expected voltage). Each differential amplifier 195 in the differential amplifier array module 193 receives the output of the expected voltage generating means 60 and the output of an output terminal (Y1-YM) of the DUT 191. The differential amplifier array module 193 (differential amplifiers 195) amplifies difference voltages between the output of the expected voltage generating means 60 and the outputs of respective output terminals (Y1-YM) of the DUT 191, and then provides the difference voltages to the semiconductor testing apparatus 192 (ch1-chM).
The DUT 191 to be tested is, for example, a liquid crystal driving apparatus (liquid crystal driving LSI) which comprises M output terminals for liquid crystal driving and which comprises n-gradation level DACs 194 each for selecting one from n voltage levels and thereby outputting the voltage level through an output terminal. The semiconductor testing apparatus 192 provides an input signal (not shown) to the DUT 191, and thereby causes the DUT 191 to generate a predetermined gradation output voltage in the M output terminals. Each of the gradation output voltages from the M output terminals is simultaneously inputted to one input terminal of each differential amplifier 195 provided in the differential amplifier array module 193. On the other hand, an expected voltage for the gradation output voltage is provided from the expected voltage generating means 60 to the other input terminal of each differential amplifier 195. The differential amplifier array module 193 acquires the difference voltages of the gradation output voltages outputted from the M output terminals of the DUT 191 relative to the expected voltage outputted from the expected voltage generating means 60, that is, deviations from the expected voltage.
For the purpose of precise comparison and determination of the difference voltages, the difference voltages are first amplified by amplifying means (not shown; see amplifiers 8 in FIG. 21) provided in the differential amplifier array module 193. The M amplified voltages (Y1-YM) are outputted through the output terminals of the differential amplifier array module 193 into the tester channels (ch1-chM) of the semiconductor testing apparatus 192.
The semiconductor testing apparatus 192 comprises two pieces of voltage measuring means. These are a DC measurement unit (not shown) for measuring a DC voltage level with precision and the above-mentioned comparing section 196 provided in the tester channels. The comparing section 196 performs mainly a functional operation test, and hence has a lower precision in voltage measurement than the DC measurement unit. Thus, in an ordinary configuration, the comparing section 196 cannot perform the above-mentioned precise comparison and determination of the difference voltages. However, the above-mentioned amplification of the difference voltages using the amplifying means permits the comparing section 196 to perform the precise comparison and determination. As such, the use of the differential amplifier array module 193 in the measurement realizes a test with a similar or higher precision in comparison with the prior art.
FIG. 21 is a diagram illustrating a prior art semiconductor test system similar to that of FIG. 20. A DUT; subtractors 6 and amplifiers 8; expected voltage generating means 60; and a semiconductor testing apparatus 15 shown in FIG. 21 correspond respectively to the DUT 191, the differential amplifiers 195 (differential amplifier array module 193), the expected voltage generating means 60, and the semiconductor testing apparatus 192 of FIG. 20. A digital comparing section 11 corresponds to the comparing section 196. The semiconductor testing apparatus 15 further comprises tester controlling means 40 and a peripheral block section 12. The tester controlling means 40 performs necessary processes in response to signals (D1-DM) provided from the digital comparing section 11.
In the test performed by the apparatuses of FIGS. 20 and 21, when the expected voltage for each gradation level is outputted from the expected voltage generating means 60, an expected voltage having been set in advance according to a xcex3-characteristic specification or the like is calculated by a program, whereby the data obtained as the result of this calculation is transferred to the expected voltage generating means 60, and whereby expected voltages are outputted sequentially.
FIG. 22 is a block diagram showing schematically the circuit block of the expected voltage generating means in the prior art semiconductor test systems of FIGS. 20 and 21. Here, the expected voltage generating means 60 is described as the expected voltage generating means 60 in FIG. 20 and as the expected voltage generating means 60 in FIG. 21. In the expected voltage generating means 60, data transferred from the semiconductor testing apparatus 192 or the semiconductor testing apparatus 15 is inputted to controlling means 65, while data which needs to be stored temporarily is stored in storing means 66. Each piece of the data is converted into an expected voltage corresponding thereto by a DAC 61, and then outputted as an expected voltage (61a) to the differential amplifier array module 193 or the subtractor 6.
FIG. 23 is a waveform diagram showing the behavior of the gradation output voltage. This diagram shows: an expected gradation voltage waveform xe2x80x9caxe2x80x9d outputted from the expected voltage generating means 60 to the differential amplifier array module 193 (differential amplifiers 195) or the subtractors 6; and a gradation output voltage waveform xe2x80x9cbxe2x80x9d outputted from the DUT (191) serving as a liquid crystal driving apparatus. The gradation output voltage outputted from the liquid crystal driving apparatus has deviation voltages, for example, of xcex94V1, xcex94V2, and xcex94V3 relative to the expected voltages. In the test of the liquid crystal driving apparatus (DUT), it is tested whether these deviation voltages xcex94V fall within a predetermined voltage range, and whether these deviation voltages xcex94Vi (i=1 through n) are uniform among the output terminals.
FIG. 24 is a block diagram showing schematically the circuit block of output voltage testing means of a prior art semiconductor testing apparatus. The output voltage testing means 50 is incorporated in the comparing section 196 of the semiconductor testing apparatus 192 of FIG. 20, and performs so-called digital determination. The output voltage testing means 50 comprises: test voltage inputting means 51 for inputting a voltage to be tested which is outputted from an output terminal (not shown) of a liquid crystal driving apparatus (DUT); a high level comparator 52 serving as high level comparing means for comparing the voltage to be tested with a high level reference voltage; a low level comparator 53 serving as low level comparing means for comparing the voltage to be tested with a low level reference voltage; VOH inputting means 54 for providing a high level comparison voltage VOH to the high level comparator 52; VOL inputting means 55 for providing a low level comparison voltage VOL to the low level comparator 53; and comparison result outputting means 56 for outputting the comparison results in the high level comparator 52 and the low level comparator 53 as high level comparison result data DMH and low level comparison result data DML, respectively. Each of the high level comparator 52 and the low level comparator 53 is composed of a comparator.
A tester controlling means 40 arranged outside the output voltage testing means 50 provides digital data of high level comparison voltage generation data IVH corresponding to the high level comparison voltage VOH, to a DAC 106. The DAC 106 converts the digital data into an analogue voltage of high level comparison voltage VOH, and then provides the high level comparison voltage VOH to the VOH inputting means 54. Similarly, the tester controlling means 40 provides digital data of the low level comparison voltage generation data IVL corresponding to the low level comparison voltage VOL, to a DAC 107. The DAC 107 converts the digital data into an analogue voltage of low level comparison voltage VOL, and then provides the low level comparison voltage VOL to the VOL inputting means 55. The tester controlling means 40 comprises plural pieces of output voltage testing means 50 in a number, for example, of 200-500 channels corresponding to the number of output terminals of the DUT (in the figure, only one channel chM is shown).
Nevertheless, according to the configuration of the prior art output voltage testing means 50 shown in FIG. 24, in the measurement of the gradation output voltage from the liquid crystal driving apparatus (DUT), the determination of the gradation output voltage is performed by digital signal processing of the comparison result output data from the comparing means (comparators) provided in the semiconductor testing apparatus. Accordingly, the precision in the voltage measurement still depends on the precision of the comparators. For the purpose of improving the precision in the measurement and determination, the comparators can be replaced by expensive ones having a higher precision (for example, 1 mV or better). Nevertheless, the semiconductor testing apparatus requires comparators in a number proportional to the number of output terminals of the liquid crystal driving apparatus (DUT). This causes the problem that the semiconductor testing apparatus itself becomes extremely expensive.
For example, in the case of a 64-gradation level (6-bit color gradation) liquid crystal driving apparatus having 384 output terminals, a voltage measurement precision of 20-10 mV or the like is sufficient in the comparators (for example, 3-5 V is divided by 64 gradation levels, while a margin of xc2xc or the like of the value is assumed). In contrast, in the case of a 256-gradation level (8-bit color gradation) liquid crystal driving apparatus having 384 output terminals, a voltage measurement precision of 5.0-2.5 mV or the like is necessary in the comparators (for example, 3-5 V is divided by 256 gradation levels, while a margin of xc2xc or the like of the value is assumed). This is because for the purpose of maintaining the display quality of the liquid crystal display panel, a variation among the output terminals with respect to the gradation output of the liquid crystal driving apparatus needs to be maintained within xc2xc or the like of the voltage per gradation level.
That is, in the case that the supply voltage is 5 V, in a 64-gradation level liquid crystal driving apparatus, the voltage difference between adjacent gradation levels is approximately 80 mV, although this value depends on the xcex3-correction. Accordingly, a variation of approximately 20 mV or less needs to be guaranteed among the output terminals. Thus, the voltage measurement precision necessary in the comparators is as follows. For example, in the semiconductor test system of FIG. 20, when the difference voltage between the gradation output voltage and the expected voltage is amplified by a factor of 10 in the differential amplifier 195, a difference voltage of 20 mV (corresponding to the guaranteed variation voltage) is amplified into 200 mV. Thus, when the precision permits accurate measurement of a 20 mV which is {fraction (1/10)} of the 200 mV, the guaranteed variation voltage is realized. That is, a precision permitting accurate measurement of a 20 mV which is {fraction (1/10)} of the amplified voltage of 200 mV is necessary. This measurement precision agrees with the specification of the comparators of testers used widely in these days.
The DAC 61 provided in the expected voltage generating means 60 (see FIG. 22) is composed of a digital-to-analogue converter having a resolution of 2 mV or better. Nevertheless, in addition to this resolution, the DAC has an offset error of a few mV and a gain error of 0.01% or the like. Thus, there has been the problem that these errors prevent higher precision measurement of the gradation output voltage which is necessary for liquid crystal driving apparatuses with 256, 512, or greater gradation levels.
Similarly to the above-mentioned discussion, a 256-gradation level liquid crystal driving apparatus requires a measurement precision of 5 mV or the like. Further, a 512-gradation level liquid crystal driving apparatus requires a measurement precision of 2.5 mV or the like. That is, in liquid crystal driving apparatuses with gradation levels exceeding 256, the precision in the voltage measurement becomes insufficient as long as the prior art testing method is used. This has caused the problems of yield degradation and shipment quality degradation.
Further, comparators having a higher precision and a response speed of a few tens MHz are special order items, in general. Accordingly, the adoption of such new special components causes an increase in the component cost, and hence is undesirable. In order to meet demands for higher image quality in liquid crystal display panels, the number of pixels in display panels tends to increase year by year, and so does the number of output terminals per a liquid crystal driving apparatus. Accordingly, the cost of each comparator is desired to be reduced more seriously. Thus, the above-mentioned solution of adopting special comparators which causes an increase in the tester price is not desirable. The adoption of special comparators further causes the problem that such special comparators based on a special order have a difficulty in availability and hence cause a problem in emergency maintenance service.
The invention has been made with considering such a situation. An object of the invention is to provide a semiconductor testing apparatus and a semiconductor testing method which permit an apparatus having an inexpensive configuration to perform, with precision, the acceptance-or-rejection determination and measurement test of a semiconductor integrated circuit (such as a semiconductor integrated circuit for liquid crystal driving) having a large number of output terminals each for outputting a multi-gradation level output voltage.
A semiconductor testing apparatus according to the invention tests the gradation output voltage characteristics of a semiconductor integrated circuit for outputting a gradation output voltage through each of a plurality of output terminals, and comprises plural pieces of output voltage testing means each corresponding to each of said output terminals. Said output voltage testing means comprises: test voltage inputting means for inputting a voltage to be tested which is obtained from a gradation output voltage; comparison voltage generating means for generating a comparison voltage to be compared with the voltage to be tested, on the basis of comparison voltage generation data provided from comparison voltage generation data inputting means; and comparing means for comparing the voltage to be tested with the comparison voltage. Said comparison voltage generation data is generated by adding common comparison voltage generation data shared with the other pieces of the output voltage testing means to individual comparison voltage generation data provided for each piece of the output voltage testing means in order to correct an intrinsic error in each piece of the comparing means.
In a semiconductor testing apparatus according to the invention, said comparison voltage generation data inputting means comprises: common comparison voltage generation data inputting means for inputting common comparison voltage generation data; individual comparison voltage generation data inputting means for inputting individual comparison voltage generation data; and an adder for adding the common comparison voltage generation data to the individual comparison voltage generation data; wherein the result of the addition in said adder is provided as said comparison voltage generation data to the comparison voltage generating means.
In a semiconductor testing apparatus according to the invention, said comparing means comprises: a high level comparator for comparing and detecting whether the voltage to be tested is at or below an upper allowable limit relative to the comparison voltage or not; and a low level comparator for comparing and detecting whether the voltage to be tested is at or above a lower allowable limit relative to the comparison voltage or not; wherein each piece of the comparison voltage generation data inputting means and each piece of the comparison voltage generating means are provided corresponding to each of a high level comparator and a low level comparator.
A semiconductor testing apparatus according to the invention comprises correction data generating means for setting and storing said individual comparison voltage generation data and for outputting the individual comparison voltage generation data to the comparison voltage generation data inputting means. In a semiconductor testing apparatus according to the invention, each piece of said correction data generating means is provided corresponding to each piece of the output voltage testing means. A semiconductor testing apparatus according to the invention comprises: expected voltage generating means for outputting an expected gradation voltage corresponding to said gradation output voltage; and voltage difference detecting means for acquiring the difference between the gradation output voltage and the expected gradation voltage and then outputting the difference to the test voltage inputting means.
In a semiconductor testing apparatus according to the invention, said expected voltage generating means comprises: ideal value input data storing means for storing ideal value input data for the expected gradation voltage; correction value input data storing means for storing correction value input data for correcting the expected gradation voltage; an adder for adding the ideal value input data to the correction value input data and then outputting the expected voltage data; and expected voltage outputting means for generating an expected gradation voltage based on the expected voltage data and then providing the expected gradation voltage to the voltage difference detecting means.
In a semiconductor testing apparatus according to the invention, each of said comparison voltage generating means and said expected voltage outputting means comprises a digital-to-analogue converter, wherein the digital-to-analogue converter provided in the expected voltage outputting means has a higher resolution than the digital-to-analogue converter provided in the comparison voltage generating means. A semiconductor testing apparatus according to the invention comprises amplifying means for amplifying an output of said voltage difference detecting means and for providing the amplified output to the test voltage inputting means.
A semiconductor testing apparatus according to the invention comprises, in a position between said amplifying means and said test voltage inputting means, a first correction switch a common terminal of which is connected to the test voltage inputting means, a first independent terminal of which is connected to the output terminal of the amplifying means, and a second independent terminal of which is connected to a fixed potential terminal, wherein said first correction switch connects the test voltage inputting means to the amplifying means when said gradation output voltage is tested, and connects the test voltage inputting means to the fixed potential terminal when the individual comparison voltage generation data is to be set and corrected in order to correct said comparison voltage.
A semiconductor testing apparatus according to the invention comprises, in a position between said semiconductor integrated circuit and said voltage difference detecting means, a second correction switch a common terminal of which is connected to the voltage difference detecting means, a first independent terminal of which is connected to the output terminal of the semiconductor integrated circuit, and a second independent terminal of which is connected to precision voltage generating means, wherein said second correction switch connects the voltage difference detecting means to the semiconductor integrated circuit when said gradation output voltage is to be tested, and connects the voltage difference detecting means to the precision voltage generating means when said expected voltage generating means is to be corrected.
In a semiconductor testing apparatus according to the invention, said semiconductor testing apparatus is constructed as a module. In a semiconductor testing apparatus according to the invention, said semiconductor testing apparatus comprises an integrated circuit driving section for driving said semiconductor integrated circuit. In a semiconductor testing apparatus according to the invention, said semiconductor integrated circuit is composed of a semiconductor integrated circuit for liquid crystal driving.
A semiconductor testing method according to the invention is a semiconductor testing method for testing the gradation output voltage characteristics of a semiconductor integrated circuit for outputting a gradation output voltage through each output terminal, comprising the steps of providing a voltage to be tested which is based on the difference between the gradation output voltage and an expected gradation voltage corresponding to an ideal value for the gradation output voltage, into plural pieces of output voltage testing means each provided corresponding to each of the output terminals; and comparing the voltage to be tested with a comparison voltage and thereby testing the gradation output voltage by the output voltage testing means; wherein said comparison voltage is corrected in each piece of the output voltage testing means in order to correct the intrinsic error of a digital-to-analogue converter provided in each piece of the output voltage testing means.
In a semiconductor testing method according to the invention, said expected gradation voltage is corrected in order to correct the intrinsic error of a digital-to-analogue converter provided in expected voltage generating means for generating an expected gradation voltage.
The configuration according to the invention comprises: comparison voltage generating means for generating a comparison voltage (such as a reference voltage specifying an allowable range for a multi-gradation level output voltage) which is to be compared with a voltage to be tested (such as the difference voltage between the multi-gradation level output voltage and an expected gradation voltage), on the basis of comparison voltage generation data provided from comparison voltage generation data inputting means; and comparing means for comparing the voltage to be tested with the comparison voltage; wherein the comparison voltage generation data is generated by adding common comparison voltage generation data shared with the other pieces of output voltage testing means to individual comparison voltage generation data provided for each piece of output voltage testing means in order to correct an intrinsic error in each piece of comparing means. This permits individual correction of the intrinsic error in each piece of comparing means, and thereby provides a semiconductor testing apparatus and a semiconductor testing method with precision at a low cost.
According to the invention, expected voltage generating means comprises: ideal value input data storing means for storing ideal value input data for the expected gradation voltage; and correction value input data storing means for storing correction value input data for correcting the expected gradation voltage. This permits the correction of an error in the expected voltage generating means, and thereby provides a semiconductor testing apparatus and a semiconductor testing method with precision at a low cost.
The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings.